(a) Field of the Invention
The present invention relates to a phase-locked loop based frequency synthesizer and a method of operating the same.
(b) Description of the Related Art
Frequency synthesizers are widely used in modern digital communications. A Phase Locked Loop (PLL) is used as means for implementing a frequency synthesizer at an RF output stage of a digital communication system.
FIG. 1 is a view showing a conventional PLL-based frequency synthesizer.
As shown in FIG. 1, the PLL-based frequency synthesizer includes a phase frequency detector (PFD) 10, a charge pump (CP) 20, a loop filter 30, a voltage controlled oscillator (VCO) 40, and a frequency divider 50.
The PFD 10 detects a phase difference and a frequency difference between a reference frequency Fref and a comparison frequency Fdiv, and outputs a corresponding pulse signal. The CP 20 generates a control current corresponding to a pulse signal output from the PFD 10 and outputs it to the LP 30. The LP 40 removes high frequency components from the control current, and outputs a control voltage proportional to the control current from the VCO 40. The VCO 40 outputs an output frequency Fout proportional to a control voltage output from the LP 40. The frequency divider 50 divides the output frequency Fout of the VCO 40 at a frequency division ratio N and feeds it back as a comparison frequency Fdiv to the PFD 10.
As a result of this negative feedback operation, the PLL-based frequency synthesizer operates such that the reference frequency and the same phase. Therefore, the output frequency Fout of the VCO 40 is expressed as Equation 1.Fout=N*Fref  [Equation 1]
Where N is the frequency division rate of the frequency divider 50 (N is a positive integer).
Therefore, the PLL-based frequency synthesizer can obtain an output frequency Fout N times higher than the reference frequency Fref. Due to this reason, the output frequency Fout can be changed at N intervals. The PLL-based frequency synthesizer has to lower the reference frequency Fref in order to increase the resolution. However, once the reference frequency Fref is lowered, the cutoff frequency of the LP 40 needs to be lowered as well. As a result, the in-band noise increases, and the lock time increases.
To make up for this drawback of such an integer-N frequency synthesizer, fractional-N PLLs were suggested. Among the fractional-N PLLs, a fractional-N PLL using a sigma-delta modulator has a fractional frequency division ratio, rather than an integer frequency division ratio. Accordingly, the resolution of the frequency synthesizer can be increased without reducing the reference frequency Fref. Incidentally, a quantization noise generated by the sigma-delta modulator is a function of the operating frequency of the sigma-delta modulator, which resultantly functions to limit the cut-off frequency of the LP 40. In other words, if the cut-off frequency of the LP 40 is high, noise of the sigma-delta modulator is not filtered but transferred to the output frequency Fout, thereby degrading the overall phase noise characteristics.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.